`include "code\source\P4\Crc16.v"

module test_Crc16;

initial begin
    $dumpfile("./release/test_Crc16.vcd");
    $dumpvars(0, test_Crc16);
end

reg clk, rst_n, clear, din, din_valid;
wire [15: 0] crc;

Crc16 #(
    .Initial (0 )
) u_Crc16(
    .clk       (clk       ),
    .rst_n     (rst_n     ),
    .clear     (clear     ),
    .din       (din       ),
    .din_valid (din_valid ),
    .crc       (crc       )
);

initial clk = 0;
always #5 clk = ~clk;

initial begin
    rst_n <= 0;
    din <= 0;
    clear <= 0;
    #10
    rst_n <= 1;
    #20
    din_valid <= 1;
    #30
    din <= 1;
    #10
    din <= 0;
    #20
    din <= 1;
    #10
    din <= 0;
    #30
    din <= 1;
    #20
    din <= 0;
    #10
    din <= 1;
    #10
    din <= 0;
    #20
    din_valid <= 0;
    #50
    $finish;
end

    
endmodule